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CXB1586AR
10 Bit 1.0625 Gbaud Transceiver For the availability of this product, please contact the sales office.
Description The CXB1586AR is a transceiver IC with a built-in PLL for Fibre Channel. For a receiver 1.0625 Gbaud serial data is received and output it as the 10-bit parallel data; for transmitter 1.0625 Gbaud 10bit parallel data is output as the serial data. Features * Transmitter and receiver in a single chip * ANSI X3T11 Fibre Channel compatible (FC_0) at 1.0625 Gbaud * Conforms to 10-bit interface specification * TTL / ECL compatible * Single +3.3 V power supply * * * * * PLL for clock generation and clock / data recovery Byte sync detector (positive character of comma) Local loop back circuit Low power consumption (0.8 W typ.) 64-pin plastic LQFP package (10 mm x 10 mm) 64 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage VCC -0.3 to 4 V * Operating temperature Topr -55 to +70 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD to 1109 mW Operating Conditions Supply voltage
VCC
3.14 to 3.46
V
Applications 1.0625 Gbaud Fibre channel Structure Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E97319C83-TE
CXB1586AR
LCKREF
Block Diagram
LBEN
SDOUT
TX0-9
10 DQ
10
Pin
P/S Conv.
Sout SDOUT
REFCLK
REFCLK (106.25M)
TX_PLL
LCLK (106.25M) TCLK (1.0625G)
LPF_TX0
LPF_TX1 RDATA 1 0 PX_PLL
SDIN
SDIN
RCLK (1.0625G)
RX0-9
10 S/P Conv.
1/10
LPF_RX0
LPF_RX1
BYTSYNC BYTSYNCEN RBC1 RBC0 1/2 FCLK (106.25M)
48 LPF_RX1 VCCP_RX VEEP_RX SDIN VCCE SDIN VCCG VEEG VCCG VEEG VCCG VCCE SDOUT SDOUT VCCE VEEE 49
LPF_RX0 BYTSYNC VEET RX0 RX1 RX2 VCCT RX3 RX4 RX5 RX6 VCCT RX7 RX8 RX9 VEET
40 33 32 VEET RBC0 RBC1 VCCT VCCG LCKREF TEST VEEG BYTSYNCEN VCCG REFCLK VEEG VCCG LBEN VCCP_TX LPF_TX1 56 24 64 1 8 16 17
Pin Configuration (Top View)
VEET TX0 TX1 TX2 VCCG TX3 TX4 TX5 TX6 VCCG TX7 TX8 TX9 VEET VEEP_TX LPF_TX0
--2--
CXB1586AR
DC Characteristics Item TTL high level input voltage TTL low level input voltage TTL high level input current TTL low level input current TTL high level output voltage TTL low level output voltage ECL high level input voltage ECL low level input voltage ECL peak-to-peak differential input voltage swing ECL high level output voltage ECL low level output voltage ECL peak-to-peak differential output voltage swing Current consumption Power dissipation Symbol VIH_T VIL_T IIH_T IIL_T VOH_T VOL_T VIH_E VIL_E VIS_E 1) VOH_E VOL_E VOS_E 2) ICC PD Min. 2 0 -400 2.2 VCC-1.17 VCC-1.81 400 VCC-1.05 VCC-1.81 1200 250 825 Typ.
(under the recommended conditions) Max. 5.5 0.8 20 Unit V V A A V V V V mV V V mV mA mW Output pins open Output pins open Conditions
0.5 VCC-0.88 VCC-1.48 2000 VCC-0.81 VCC-1.55 1900 320 1109
Vin=VCC Vin=0 IOH=-0.4 mA IOL=2 mA
AC coupling input 50 terminated to VCC-2 V 50 terminated to VCC-2 V
Note : 1) ECL peak-to-peak differential input voltage swing 2) ECL peak-to-peak differential output voltage swing
Voltage VCC signal-in+ VIH_E
Vi1
Vi2
VIL_E signal-in- VEE=GND 1) VIS_E= |Vi1| + |Vi2| Voltage VCC signal-out+ VOH_E
Vo1
Vo2
VOL_E signal-out- VEE=GND 2) VOS_E= |Vo1| + |Vo2|
--3--
CXB1586AR
AC Characteristics Item TTL input rise time of TX TTL input fall time of TX TTL input rise time of REFCLK TTL input fall time of REFCLK TTL output rise time TTL output fall time ECL output rise time ECL output fall time REFCLK period REFCLK duty cycle REFCLK frequency tolerance TX setup time to REFCLK TX hold time to REFCLK RX setup time to RBC RX hold time to RBC Skew between RBC0 and 1 RBC duty cycle Deterministic jitter (p-p) Random jitter (p-p) Jitter tolerance Symbol Tir_TX Tif_TX Tir_REF Tif_REF Tor_T Tof_T Tor_E Tof_E Tp_REF 9.26 DC_REF 40 Ftol_REF -100 Ts_TX 2 Th_TX 1.5 Ts_RX 3 Th_RX 1.5 Tsk_RBC Tp/2-0.5 DC_RBC 40 DJ RJ JT Min. 0.7 0.7 0.7 0.7
(under the recommended operating conditions) Typ. Max. 4.8 4.8 2.4 2.4 3.5 3.5 400 400 9.56 60 100 Unit ns ns ns ns ns ns ps ps ns % ppm ns ns ns ns ns % UI UI UI Conditions 0.8 V to 2.0 V 2.0 V to 0.8V 0.8 V to 2.0 V 2.0 V to 0.8 V 0.8 V to 2.0 V, CL=10 pF 2.0 V to 0.8 V, CL=10 pF 20 % to 80 %, CL=2 pF 20 % to 80 %, CL=2 pF
9.41
Tp/2
Tp/2+0.5 60 0.07 0.23 0.7
0.02 0.18
Tp is period of RBC in frequency lock Serial data output (k28.5) Serial data output Serial data input
--4--
CXB1586AR
PLL AC Characteristics Item Frequency acquisition time of TX and RX PLL Bit synchronization time of RX PLL Symbol Tfa Tbs Min.
(under the recommended operating conditions) Typ. Max. 500 2500 Unit s bit Conditions Loop damping capacitor=0.01 F
Absolute Maximum Ratings Item Power supply voltage (Except VCCT5) TTL DC input voltage ECL DC input voltage ECL peak-to-peak differential input voltage swing TTL output current (High level) TTL output current (Low level) ECL output current Ambient temperature Storage temperature Symbol VCC VI_T VI_E VIS_E IOH_T IOL_T IO_E Ta Tstg Min. -0.3 -0.5 VCC-2 -4 -20 0 -30 -55 -65 Typ.
(VEEE, VEET, VEEG, VEEP=GND) Max. 4 5.5 VCC 4 0 20 0 70 150 Unit V V V V mA mA mA C C Remarks
Under bias
Recommended Operating Conditions Item Supply voltage (Including VCCT5) Ambient temperature Symbol VCC Ta Min. 3.135 0 Typ. 3.3 Max. 3.465 70 Unit V C Remarks
--5--
CXB1586AR
Pin description Pin No. 1, 14, 32, 33, 46 2-4, 6-9, 11-13 5, 10, 20, 23, 28, 55, 57, 59 15 16 17 18 Symbol VEET TX0-9 Type PS I_TTL Description Ground for TTL output : Normally 0 V. Parallel transmit data inputs to be serialized. TX0 is serialized first and TX9 is last. Power supply for internal logic gates : Normally 3.3 V. Ground for TX PLL : Normally 0 V. Connect to external loop filter of TX PLL. Connect a capacitor (0.01 F) between LPF_TX0 and LPF_TX1. Power supply for TX PLL : Normally 3.3 V. Loop back enable : When high, TX serializer output internally connects to RX deserializer input, SDOUT/SDOUT is held low/high, and SDIN/SDIN is disabled. When low, SDOUT/SDOUT and SDIN/SDIN are enabled. Power supply for internal logic gates : Normally 0 V. Reference clock for PLL and transmit byte clock (106.25 MHz). Supplied by the host system. Byte synchronization enable : When high, the positive comma character (0011111) detection circuit is enabled to establish byte synchronization (see Timing Chart). Test pin : Normally 3.3 V or open. Lock to reference clock : An active low input. LCKREF forces the PLL lock to the REFCLK supplied by the host system. Power supply for TTL output : Normally 3.3 V. Receive byte clocks recovered from the serial data (53.125 MHz). These clocks are 180 degrees out of phase, and RX0-9 are alternatively clocked on the rising edge of these clocks (see Timing Chart) Parallel receive data output : RX0 is received first and RX9 is last. Byte synchronization indicator : High when a positive comma character is detected (see Timing Chart) Connect to external loop filter of RX PLL. Connect a capacitor (0.01 F) between LPF_RX0 and LPF_RX1. Power supply for RX PLL : Normally 3.3 V. Ground for RX PLL : Normally 0 V. --6-- Equivalent circuit -- (a)
VCCG VEEP_TX LPF_TX0 LPF_TX1 VCCP_TX
PS PS EX PS
-- -- (e) --
19
LBEN
I_TTL
(a)
21, 25, 56, 58 22
VEEG REFCLK
PS I_TTL
-- (a)
24
BYTSYNCEN TEST LCKREF VCCT RBC1 RBC0
I_TTL
(a)
26 27 29, 37, 42 30 31 34-36, 38-41, 43-45 47 48 49 50 51
I_TTL I_TTL PS
(a) (a) --
O_TTL
(b)
RX0-9
O_TTL
(b)
BYTSYNC LPF_RX0 LPF_RX1 VCCP_RX VEEP_RX
O_TTL EX PS PS
(b) (e) -- --
CXB1586AR
Pin No. 52 54 53, 60, 63 61 62 64
Symbol SDIN SDIN VCCE SDOUT SDOUT VEEE
Type I_ECL (Diff.) PS O_ECL (Diff.) PS
Description Serial receive data inputs : These inputs are enabled when LBEN is low. Power supply for ECL output : Normally 3.3 V Serial transmit data output : These outputs are enabled when LBEN is low. When LBEN is high, SDOUT/SDOUT is held to low/high. Ground for ECL output : Normally 0 V.
Equivalent circuit (c) -- (d)
--
Pin Type Definition Type PS I_TTL O_TTL I_ECL O_ECL EX Definition Power supply or ground Input TTL Output TTL Input ECL Output ECL External circuit node
--7--
CXB1586AR
Equivalent Circuit
VCCG
VCCT3
TTL-OUT TTL-IN
VEET (a) TTL input
VEET (b) TTL output
VEET
VCCE
VCCG
VCCE
ECL-IN VCCE - 1.3V ECL-IN
ECL-OUT
ECL-OUT
VEEE (c) ECL input
VEEG (d) ECL output
VEEE
VCCP LPF0 LPF1
VEEP2 (e) LPF0/LPF1-pin
VEEP1
--8--
CXB1586AR
Timing Chart
Tir_TX
Tif_TX
2.0V TX_a TX_b 1.4V 0.8V TX0 - 9 Ts_TX Th_TX 2.0V 1.4V 0.8V REFCLK Tir_REF Tif_REF
TX0_a TX1_a TX2_a TX3_a TX4_a TX5_a TX6_a TX7_a TX8_a TX9_a TX0_b TX1_b TX2_b
SDOUT
(a) Transmiter Section Timing
Tskew 2.0V HOLD 1.4V 0.8V RBC0 Tor_T Tof_T 2.0V HOLD 1.4V 0.8V RBC1 Ts_RX Th_RX 2.0V COMMA (+) VALID DATA COMMA (+) VALID DATA VALID DATA 1.4V 0.8V RX0 - 9 Ts_RX Th_RX 2.0V 1.4V 0.8V BYTSYNC
(b) Receiver Section Timing
--9--
CXB1586AR
Notes on Operation 1. External loop filters for PLLs The CXB1586AR has two PLLs. One is for the transmitter and locks to the reference clock from REFCLK input pin. Another one is for the receiver and locks to the received serial data from SDIN/SDIN input pins. They need external capacitors for the their loop filters. Typical values of the external capacitors are indicated below.
C2
48 49
17
16 C1 : 0.01F C2 : 0.01F C1
2. Example of power supply circuit
VCCT
VCCG VCCE
VCCP
3.3V 22F 0.1F VEET 22F 0.1F VEEG VEEE 22F 0.1F VEEP
--10--
CXB1586AR
3. High-speed ECL differential input The high-speed ECL differential input pins are biased to VBB (VCC-1.3V) via a 18 k resistor in the IC. See the figures below for ECL differential input methods.
VCC=3.3V, VEE=GND VCC=3.3V, VEE=GND VBB (VCC-1.3V)
160 3.3V ECL output buffer
160
18k
ECL differential input buffer VCC=3.3V, VEE=GND VBB (VCC-1.3V)
(a) ECL differential signal from 3.3V ECL output buffer
VCC=GND, VEE=-4.5V 0.01F
330 ECL 100K output buffer
0.01F 330 VEE
18k
ECL differential input buffer VCC=3.3V, VEE=GND VBB (VCC-1.3V)
(b) ECL differential signal from ECL 100K output buffer
0.01F 75 TRANS. LINE 0.01F 75
75
18k
ECL differential input buffer VCC=3.3V, VEE=GND VBB (VCC-1.3V)
(c) differential signal from 75 transmission line (AC/DC termination)
0.01F 75 TRANS. LINE 0.01F 75 0.01F
75
18k
ECL differential input buffer
(d) differential signal from 75 transmission line (AC termination)
--11--
18k
18k
18k
18k
CXB1586AR
VCC=3.3V, VEE=GND VBB (VCC-1.3V) 0.01F 50 TRANS. LINE 0.01F 50 VTT (VCC-2V)
50
18k
ECL differential input buffer VCC=3.3V, VEE=GND VBB (VCC-1.3V)
(e) ECL differential signal from 50 transmission line
0.01F
0.01F
18k
ECL differential input buffer
50 TRANS. LINE
50
VTT (VCC-2V)
(f) ECL single signal from 50 transmission line
--12--
18k
18k
CXB1586AR
Electrical Characteristics Measurement Circuit
II_T
Device under test TTL_IN TTL_OUT IO_T
A
VI_T
V VO_T
(a) TTL I/O DC characteristics measurement circuit
Device under test Probe Pulse generator TTL_IN TTL_OUT CL Oscilloscope
CL=10pF (including the probe capacitance)
(b) TTL I/O AC characteristics measurement circuit
II_E
Device under test ECL_IN ECL_OUT 50
A
VI_TE
V VO_E
VCCE-2V
(c) ECL I/O DC characteristics measurement circuit
VCCE-2V 50 Pulse generator 50 0.1F 0.1F Device under test ECL_IN ECL_IN ECL_OUT ECL_OUT
VCCE-2V 50 Oscilloscope 50 VCCE-2V CL2pF (input capacitance of the measurement equipment and floating capacitance)
VCCE-2V 50 Transmission line
(d) ECL I/O AC characteristics measurement circuit
--13--
CXB1586AR
VCCE-2V 50 531.25MHz 50 0.1F Device under test 0.1F SDIN Pulse pattern generator SDIN RX0-9 parallel data 10bit
VCCE-2V Oscilloscope SDOUT 50 TRIG VCCE-2V VCCE-2V 531.25MHz 50 SDOUT
REFCLK
TX0-9
106.25MHz
(e) TX random jitter measurement circuit
Attenuate VCCE-2V 50 1.0625Gbps CLKOUT CLKOUT DATAOUT DATAOUT Random pattern 2 ^ 7-1 or 2 ^ 23-1 50 0.1F Device under test 0.1F SDIN SDIN RX0-9 parallel data 10bit
Error rate counter
VCCE-2V DATAIN
CLKIN 50 VCCE-2V 1.0625Gbps 50
SDOUT SDOUT REFCLK TX0-9
VCCE-2V Pulse pattern generator
106.25MHz
(f) Error rate measurement circuit
VCCE-2V 50 531.25MHz 0.1F SDIN SDIN 50 Jitter analyzer VCCE-2V CLKIN SDOUT 50 VCCE-2V VCCE-2V modulate 106.25MHz 531.25MHz 50 SDOUT REFCLK TX0-9 0.1F Device under test RX0-9 parallel data 10bit
CLKOUT
Pulse pattern generator
DATAOUT
(g) TX jitter transfer measurement circuit
--14--
CXB1586AR
Example of Representative Characteristics
Example of TX Rj measurement (SDOUT)
C1 = C2 = 0.01F SDIN input 1.0625Gbps (Transition Density : 100%) REFCLK input 106.25MHz
Rj = 9.6psec x : 30psec / div y : 100mV / div
TX Eye Pattern (SDOUT 1.0625GHz operation)
VOH_E
VOL_E
C1 = C2 = 0.01F SDIN input 1.0625Gbps Random pattern REFCLK input 106.25MHz x : 200psec / div y : 200mV / div
--15--
CXB1586AR
Input Template (Tx jitter transfer) 10 1
Modulation amplitude (UIp-p)
10 0
10 -1
10 -2 10 100 1k 10k 100k 1M 10M 100M REFCLK modulation frequency (Hz)
Tx Jitter Transfer 5.0
C1=C2=0.01F Ta=27C
SDIN input 1.0625Gbps (transition density : 100%) SDOUT output 531.25MHz REFCLK input 106.25MHz 0.0
Jitter Transfer (dB)
-5.0
-10.0
-15.0
-20.0 10 100 1k 10k 100k 1M 10M 100M REFCLK modulation frequency (Hz)
--16--
CXB1586AR
Error rate 10-3 10-4 10-5 10-6 SDIN input
C1=C2=0.01F Ta=27C
1.0625Gbps Random pattern 2^7-1 Random pattern 2^23-1 SDOUT output 1.0625MHz REFCLK input 106.25MHz
Error rate
10-7 2^7-1 10-8 10-9 10-10 10-11 6.0 7.0 8.0 9.0 10.0 11.0 SDIN-Vin (mV) 2^23-1
--17--
CXB1586AR
Package Outline
Unit : mm
64PIN LQFP (PLASTIC)
12.0 0.2 48 49 10.0 0.1 33 32
A 64 1 0.5 16 0.13 M + 0.2 1.5 - 0.1 17 (0.22) + 0.08 0.18 - 0.03
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 LQFP064-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.3g
--18--
0.5 0.2
(11.0)

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